The present invention relates generally to integrated circuits, and more particularly to a structure having a metal-insulator-metal capacitor in a copper damascene interconnect.
Transistors are used as the predominant switching element in both analog and digital integrated circuits (ICs). To make functional circuits, passive components such as resistors and capacitors are also required. Metal-insulator-metal (MIM) capacitors are very desirable components because they exhibit low resistance, especially with copper, low inductance, and no voltage shift.
Copper is favored for its low electric resistance. By utilizing the technique of chemical-mechanical-polishing (CMP), which is the standard means to efficiently planarize dielectric and copper surfaces in multi-level metallization schemes for ICs, dual copper damascene structures can be created. These structures can be further utilized to build a stack of intricate metallization interconnection layers.
For efficient, minimal size circuitry, it is desirable to place MIM capacitors within such a stack of intricate metallization interconnection layers. However, a capacitor has its own quality construction requirements. To form a capacitor, the dielectric between the two metal plates must not be electrically leaky. Uniformity and continuity considerations require that the dielectric interfaces with the metal plates have predictable parameters. The interfaces should be flat and clean, with good adhesion between adjacent materials. Such properties are generally difficult to achieve between a dielectric and a bare copper surface.
Also, the construction of conventional MIM capacitors typically requires two additional, costly, photomasks. Aligning them also typically requires costly space, since their usual locations are typically between existing metal patterns and even between existing metal levels.
Therefore, desirable in the art of integrated circuit designs are additional designs and structures that allow the construction of MIM capacitors without inheriting the aforesaid costly factors.